1. Field of the Invention
The present invention relates to a signal processing apparatus having a clamping capacity.
2. Related Background Art
For the solid-state image pickup apparatus, CCD has been conventionally employed because of its high S/N ratio. On the other hand, there has been developed so-called amplifying-type solid-state image pickup apparatus which is featured by the simplicity of use and the low electric power consumption. The amplifying solid-state image pickup apparatus is to guide a signal charge accumulated in a light receiving pixel to a control electrode of a transistor provided in the pixel portion and to output an amplified signal from a main electrode, and is known in various types such as an SIT image sensor utilizing an SIT (static induction transistor) as the amplifying transistor, a bipolar image sensor utilizing a bipolar transistor, a CMD utilizing a JFET (junction field effect transistor) in which the control electrode (gate) is depleted, and a CMOS sensor utilizing a MOS transistor. Intensive development is being conducted for the CMOS transistor, since it matches well with the CMOS process and allows to form peripheral CMOS circuits on a single chip. In such amplifying solid-state image pickup apparatus however, the output offset of the amplifying transistor in each pixel is different from pixel to pixel, so that a fixed pattern noise (FPN) is superposed with the output signal of the image sensor. There have been proposed various signal output circuits in order to eliminate such FPN. In the following there will be explained a representative example of such CMOS sensor.
FIG. 1 is a circuit diagram of a conventional CMOS image sensor and a readout circuit therefor, showing unit pixels 1 illustrated in a 2xc3x972 matrix arrangement for the purpose of simplicity. In FIG. 1 there are shown a photodiode 2 for accumulating a signal charge by receiving light, a MOS transistor 3 for amplifying the signal charge, a transfer MOS transistor 4 for transferring the signal charge accumulated in the photodiode 2 to the gate electrode of the MOS transistor 3, a reset MOS transistor 5 for resetting the gate electrode potential of the MOS transistor 3, and a power supply potential supply line 6 to which commonly connected are the drain electrode of the reset MOS transistor 5 and the drain electrode of the amplifying MOS transistor 3. There are also shown a selector switch MOS transistor 7 for selecting an output pixel, and a pixel output line 8. When the selector switch MOS transistor 7 is turned on, the source electrode of the amplifying MOS transistor and the output line 8 are connected whereby the signal output of a selected pixel is guided to the output line 8. A constant current supply MOS transistor 9 for feeding a constant current to the pixel output line 8, which supplies the amplifying MOS transistor 3 with a load current through the selector switch MOS transistor 7, thereby causing the amplifying MOS transistor 3 to function as a source follower and outputting to the output line 8 a potential corresponding to the gate potential of the MOS transistor 3 with a constant voltage difference. There are also shown a transfer control line 10 for controlling the gate potential of the transfer MOS transistor 4, a reset control line 11 for controlling the gate potential of the reset MOS transistor 5, a selection control line 12 for controlling the gate potential of the selecting MOS transistor 7, a constant potential supply line 13 for supplying the gate of the MOS transistor 9 with a constant potential thereby causing the MOS transistor 9 to operate in a saturation region thereby constituting a constant current supply source, a pulse terminal 14 for supplying the transfer control line 10 with a transfer pulse, a pulse terminal 15 for supplying the reset control line 11 with a reset pulse, a pulse terminal 16 for supplying the selection control line 12 with a selection pulse, a vertical scanning circuit 17 for selecting in succession rows of the pixels in a matrix arrangement, an output line 18 of the vertical scanning circuit 17, including a first row selecting output line 18-1 and a second row selecting output line 18-2, a switching MOS transistor 19 for guiding the pulse from the pulse terminal 14 to the transfer control line 10, a switching MOS transistor 20 for guiding the pulse from the pulse terminal 15 to the reset control line 11, and a switching MOS transistor 21 for guiding the pulse from the pulse terminal 16 to the selection control line 12. The gates of the MOS transistors 19, 20, 21 are connected to the row selecting output line 18, and the row of the pixels to be driven is determined by the state of the row selecting output line 18. An output readout circuit 22 of a pixel is provided with a capacitance 23 for holding a reset signal output of the pixel, a capacitance 24 for holding a photo signal output of the pixel, a switching MOS transistor 25 for turning on/off the conduction between the pixel output line 8 and the capacitance 23, a switching MOS transistor 26 for turning on/off the conduction between the pixel output line 8 and the capacitance 24, a noise output line 27 for guiding the reset output held in the capacitance 23, a signal output line 28 for guiding the signal output held in the capacitance 24, a switching MOS transistor 29 for turning on/off the conduction between the capacitance 23 and the noise output line 27, a switching MOS transistor 30 for turning on/off the conduction between the capacitance 24 and the signal output line 28, a noise output line resetting MOS transistor 31 for resetting the potential of the noise output line 27, a signal output line resetting MOS transistor 32 for resetting the potential of the signal output line 28, a power supply terminal 33 for supplying the source electrodes of the resetting MOS transistors 31, 32 with a reset potential, and a horizontal scanning circuit 34 for selecting in succession the above-mentioned capacitances 23, 24 provided in each column of the pixels in a matrix arrangement, including an output line 35-1 for selecting a first column and an output line 35-2 for selecting a second column. The output line of the horizontal scanning circuit 34 is connected to the gates of the switching MOS transistors 29, 30. There are further shown a pulse supply terminal 36 for applying a pulse to the gates of the resetting MOS transistors 31, 32, pulse supply terminals 37, 38 for respectively applying pulses to the gates of the switching MOS transistors 25, 26, a differential amplifier 39 for amplifying and outputting the differential voltage between the potential of the noise output line 27 and that of the signal output line 28, and an output terminal 40 of the differential amplifier 39.
In the following there will be explained the operation of the sensor shown in FIG. 1, with reference to a timing chart shown in FIG. 2. It is assumed that each of the MOS transistors shown in FIG. 1 is N type, which is turned on or off respectively when the gate potential is at the high or low level state. In timing pulse "PHgr"14 to "PHgr"38 in FIG. 2, the suffixes 14 to 38 respectively coincide with the numbers of the pulse input terminals shown in FIG. 1, and "PHgr"14 to "PHgr"38 indicate the pulses entering the respective input terminals.
At first the vertical scanning circuit 17 shifts the pulse "PHgr"18-1 supplied to the terminal 18-1 to the high level state to enable the operation of the first row of the pixel matrix. When the pulse "PHgr"16 applied to the terminal 16 is shifted to the high level state, the source of the amplifying MOS transistor 3 of the pixel is connected with the constant current power supply 9 through the output line 8 whereby the output of the source follower of the pixel is outputted to the output line 8. Then the pulse "PHgr"15 applied to the terminal 15 is shifted to the high level state to reset the gate of the amplifying MOS transistor 3 by the resetting MOS transistor 5, and, when the pulse "PHgr"37 applied to the terminal 37 is shifted to the high level state, the reset output of the pixel is accumulated in the capacitance 23 through the MOS transistor 25. Then the pulse "PHgr"14 applied to the terminal 14 is shifted to the high level state whereby the signal charge accumulated in the photodiode 2 is transferred, through the transfer MOS transistor 4, to the gate of the MOS transistor 3. Subsequently, when the pulse "PHgr"38 applied to the terminal 38 is shifted to the high level state, whereby a signal output superposed with the reset output of the pixel, is accumulated through the MOS transistor 26 in the capacitance 24. The reset outputs of the pixels show variety because of the fluctuation of the threshold voltage of the MOS transistors 3 of the pixels. Therefore, the difference of the outputs accumulated in the capacitances 23, 24 becomes a pure signal without the noise. With the operation of the horizontal scanning circuit 34, the pulses "PHgr"35-1, "PHgr"35-2 applied to the output lines 35-1, 35-2 are shifted to the high level state in succession, whereby the outputs accumulated in the capacitances 23, 24 of each column are guided, respectively through the MOS transistors 29, 30, to the horizontal output lines 27, 28. Prior to the shifting to the high level state of the control pulses "PHgr"35-1, "PHgr"35-2 applied to the output lines 35-1, 352, the pulse "PHgr"36 applied to the terminal 36 is shifted to the high level state to reset the horizontal output lines 27, 28 through the MOS transistors 31, 32. The pixel reset output and the signal output superposed with the pixel reset output, guided to the horizontal output lines 27, 28 are input to the differential amplifier 39, thereby outputting a pixel signal without noise, namely after the deduction of the reset level, from the output terminal 40.
In the following there will be explained, with reference to FIG. 3, a conventional signal readout circuit of another system.
In FIG. 3, there is shown a readout circuit 56 corresponding to the readout circuit 22 shown in FIG. 1, and components equivalent to those in FIG. 1 are represented by corresponding numbers. The configurations other than the readout circuit 56 and the output amplifier are the same as those in FIG. 1 and are therefore omitted in FIG. 3.
In FIG. 3, there are shown a pixel output line 8 equivalent to the output line 8 in FIG. 1, a clamp capacitance 41 for clamping the pixel output, a clamping MOS switch 42, a power supply terminal 43 for supplying a clamping potential, a terminal 44 for applying a pulse to the gate of the MOS transistor 42, a capacitance 45 for accumulating a signal output, a switching MOS transistor 46 for connecting the clamping capacitance 41 and the accumulating capacitance 45, a terminal 47 for applying a pulse to the gate of the MOS transistor 46, a MOS transistor 48 receiving the output 50 of a horizontal shift register 34 for transferring the signal accumulated in the accumulating capacitance 45, a horizonal output line 49 for transferring the signal accumulated in the accumulating capacitance 45, an amplifier 51 for amplifying and outputting the signal appearing on the horizontal output line 49, and an output terminal 52 of the amplifier 51.
The readout circuit shown in FIG. 3 operates in the following manner. The signals from the pixel are outputted, as in the first conventional example explained with reference to FIGS. 1 and 2, in the order of a reset output and a signal output which is superposed with signal charge transferred on the reset level. The MOS transistors shown in FIG. 3 are assumed to be turned on or off respectively the gate potential thereof is at the high or lower level state. Thus, when the reset output of a pixel appears on the output line 8, high level potentials are applied to the terminals 44, 47 to turn on the MOS transistors 42, 46 thereby maintaining potential of each of the clamp portion 41 and the accumulating capacitance 45 at the clamping potential supplied to the terminal 43. Then, after the terminal 44 is shifted to the low level state to turn off the MOS transistor 42, the signal output is given to the signal line 8, whereby the signal voltage appears in the accumulating capacitance 45 through the clamping capacitance 41. The terminal 47 is shifted to the low level in this state to turn off the MOS transistor 46. The signals accumulated in the capacitances 45 are outputted in succession through the amplifier 51 to the output terminal 52, according to the output of the horizontal shift register.
However, the first conventional example explained in the foregoing with reference to FIGS. 1 and 2 has been accompanied by the following drawbacks because the output potential from the pixel is directly accumulated in the accumulating capacitance and the pixel output is input to the differential amplifier under a capacitative division by the capacitance of the horizontal output line and the aforementioned accumulating capacitance.
A first drawback lies in the loss in the signal output potential. In FIG. 1, it is assumed that the pixel resetting accumulating capacitance 23 has a capacitance CTN, the pixel signal accumulating capacitance 24 has a capacitance CTS, the horizontal output line 27 has a capacitance CHN, the horizontal output line 28 has a capacitance CHS, the reset output potential for the pixel is VN, and the signal voltage superposed on the reset level of the pixel is VS. The input ports of the differential amplifier receive potentials |CTN/(CHN+CTN)|xc2x7VN and |CTS/(CHS+CTS)|xc2x7(VN+VS) resulting from the capacitative division. Since the circuit is so designed that CHN=CHS and CTN=CTS, a signal |CTS/(CHS+CTS)|xc2x7gVS without the noise component VS is output to the output terminal 40, wherein g represents the gain of the differential amplifier 39. Thus the signal output is lower than the pixel output by a factor CTS/(CHS+CTS), except for the gain g of the differential amplifier. CHS and CHN become larger as the number of pixel columns increases, so that the loss of the signal output becomes more conspicuous.
A second drawback lies in a loss in the noise eliminating ability resulting from the unevenness in the capacitances CHS and CHN and in those CTS and CTN, eventually resulting in an increased noise level. As explained in the foregoing, the input ports of the differential amplifier receive the potentials respectively corresponding to CTS/(CHS+CTS) and CTN/(CHN+CTN) times of the pixel output voltage, and, even through CTS and CTN are designed with an identical pattern, they inevitably show certain fluctuation in size in the practical fubrication. Also CTS and CTN tend to show a difference in the parasite capacitance, resulting for example from a fact that one of the output lines 27, 28 is closer to the horizontal shift register 34 while the other is farther therefrom, as will be apparent from the arrangement of such output lines shown in FIG. 1. Thus, if CTS/(CHS+CTS) and CTN/(CHN+CTN) are mutually different because of these factors, residual of the pixel reset level cancellation will be contained in the output of the differential amplifier. Since the pixel reset level is different from pixel to pixel because of the fluctuation in the threshold voltage of the MOS transistor of each pixel, such residual represents a fixed pattern noise (FPN).
A third drawback lies in the slow signal transfer to the horizontal output line. The reset output potential of a pixel is determined by the gate reset level of the MOS transistor 3 of the source follower amplifier of the pixel and the gate-source potential difference Vgs in the source follower operation. As the gate reset level is given by (VDDxe2x88x92Vth) in which VDD is the potential of the power supply line 6 in FIG. 1 and Vth is the threshold voltage of the resetting MOS transistor 5 of the pixel, the pixel reset output is given by (VDDxe2x88x92Vthxe2x88x92Vgs) which is usually at about the middle of VDD and ground level and which will be represented by VRS. Since the reference output level of the solid-state image pickup device is taken at a dark state when VS=0, namely at VRS, the potential of the resetting power supply terminal 33 for the horizontal output line is also selected at VRS. Consequently, when the high level potential VDD is applied to the gate of the transfer MOS transistor at the signal transfer from the capacitances 23, 24 to the horizontal output lines, the gate-source potential becomes (VDDxe2x88x92VRS), thus showing a higher on-resistance of the channel in comparison with a state where the gate-source potential is VDD and resulting in a slower signal transfer to the horizontal output line.
The above-described first drawback is more conspicuous in the second conventional example explained with reference to FIG. 3. More specifically, this is because the signal voltage accumulated in the capacitance 45 is subjected to a capacitative division CO/(CO+CT) on the pixel output signal voltage, wherein CO and CT are magnitudes of the capacitances 41, 45, and such signal voltage is further subjected to a capacitative division CT/(CH+CT) at the entry into the amplifier 51 wherein CH is the capacitance of the horizontal output line 49.
The second drawback, namely the generation of the fixed pattern noise resulting from the fluctuation of CT in each column, remains same also in the second conventional example.
The third drawback can however be avoided in the second conventional example by suitable selection of the clamping potential.
The object of the present invention is to provide a signal processing apparatus capable of efficient signal transfer.
The above-mentioned object can be attained, according to one aspect of the present invention, by a signal processing apparatus comprising clamp capacitance means for receiving, at one electrode thereof, first and second signals outputted from a signal source; a signal transfer transistor of which one main electrode is connected to an other electrode of the clamp capacitance means; signal accumulating capacitance means connected to an other main electrode of the signal transfer transistor; and reset means for fixing the potential of the signal accumulating capacitance means; and
control means for fixing the potential of the signal accumulating capacitance means by the reset means when the first signal is outputted from the signal source and maintaining the signal accumulating capacitance means in a floating state when the second signal is outputted from the signal source; and
while the signal charges are transferred from the clamp capacitance means through signal transfer transistor during the output of the first and second signals, controlling the signal transfer transistor in such a manner that the potential of the one main electrode thereof is different from that of the other main electrode thereby causing the signal charge to be transferred by a saturation current.
According to another aspect of the present invention, there is also provided a signal processing apparatus comprising clamp capacitance means for receiving, at one electrode thereof, a signal from a signal source; signal accumulating capacitance means of which one main electrode is connected to an other electrode of the clamp capacitance means, signal accumulating capacitance means connected to an other main electrode of the signal transfer transistor; reset means for fixing the potential of the signal accumulating capacitance means; and control means for controlling the potential of the control electrode of the signal transfer transistor in such a manner that, among the charges on the aforementioned main electrode of the signal transfer transistor at the side of the clamp capacitance means of which potential varies according to the change in the potential of the output signal from the signal source, a charge in a potential level exceeding the channel potential of the signal transfer transistor is transferred to the signal accumulating capacitance means by a saturation current or a sub-threshold current of the signal transfer transistor.
The above and other objects, features and technological advantages of the present invention will become apparent from the following detailed description of preferred embodiments of the present invention, taken in conjunction with the accompanying drawings.